Re: Can context switches be faster?

[John Richard Moser <nigelenki@comcast.net>]

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Russell King wrote:
> On Thu, Oct 12, 2006 at 11:44:56AM -0400, John Richard Moser wrote:
>> Can context switches be made faster?  This is a simple question, mainly
>> because I don't really understand what happens during a context switch
>> that the kernel has control over (besides storing registers).
> 
> They can be, but there's a big penalty that you pay for it.  You must
> limit the virtual memory space to 32MB for _every_ process in the
> system, and if you have many processes running (I forget how many)
> you end up running into the same latency problems.

Interesting information; for the rest of this discussion let's assume
that we want the system to remain functional.  :)

> 
> The latency problem comes from the requirement to keep the cache
> coherent with the VM mappings, and to this extent on Linux we need to
> flush the cache each time we change the VM mapping.

*OUCH*

Flushing cache takes time, doesn't it?  Worse, you can't have happy
accidents where cache remains the same for various areas (i.e. I1's
caching of libc and gtk) between processes.

I guess on x86 and x86-64 at least (popular CPUs) the cache is not tied
to physical memory; but rather to virtual memory?  Wikipedia:

  Multiple virtual addresses can map to a single physical address. Most
  processors guarantee that all updates to that single physical address
  will happen in program order. To deliver on that guarantee, the
  processor must ensure that only one copy of a physical address resides
  in the cache at any given time.

  ...

  But virtual indexing is not always the best choice. It introduces the
  problem of virtual aliases -- the cache may have multiple locations
  which can store the value of a single physical address. The cost of
  dealing with virtual aliases grows with cache size, and as a result
  most level-2 and larger caches are physically indexed.

    -- http://en.wikipedia.org/wiki/CPU_cache

So apparently most CPUs virtually address L1 cache and physically
address L2; but sometimes physically addressing L1 is better.. hur.

I'd need more information on this one.

  - Is L1 on <CPU of choice> physically aliased or physically tagged
    such that leaving it in place between switches will cause the CPU to
    recognize it's wrong?

  - Is L2 on <CPU of choice> in such a manner?

  - Can L1 be flushed without flushing L2?

  - Does the current code act on these behaviors, or just flush all
    cache regardless?

> 
> There have been projects in the past which have come and gone to
> support the "Fast Context Switch" approach found on these CPUs, but
> patches have _never_ been submitted, so I can only conclude that the
> projects never got off the ground.
> 

A shame.

- --
    We will enslave their women, eat their children and rape their
    cattle!
                  -- Bosc, Evil alien overlord from the fifth dimension
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