Linus,
An issue has come up in the tg3 ethernet driver, where we are seeing
data corruption on ppc64 machines that is attributable to a lack of
ordering between writes to normal RAM and writes to an MMIO register.
Basically the driver does writes to RAM and then a writel to an MMIO
register to trigger DMA, and occasionally the device then reads old
values from memory.
Do you have an opinion about whether the MMIO write in writel() should
be ordered with respect to preceding writes to normal memory?
Currently we have a sync instruction after the store in writel() but
not one before. The sync after is to keep the writel inside
spinlocked regions and to ensure that the store is ordered with
respect to the load in readl() and friends.
Paul.
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