Re: question regarding cacheline size

[Tejun Heo <htejun@gmail.com>]

Grant Grundler wrote:
> On Thu, Sep 07, 2006 at 03:19:04PM +0200, Tejun Heo wrote:
> ...
> > For MWI, it will cause data corruption.  For READ LINE and MULTIPLE, I 
> > think it would be okay.  The memory is prefetchable after all.
>
> Within the context of DMA API, memory is prefetchable by the device
> for "streaming" transactions but not for "coherent" memory.
> PCI subsystem has no way of knowing which transaction a device
> will use for any particular type of memory access. Only the
> driver can embed that knowledge.

I think using larger cacheline value should be okay for both 
prefetchable and non-prefetchable memory.  Using larger value tells the 
device to be more conservative in issuing MRL, MRW or WMI.  As Russell 
has pointed out, cacheline-wrapping access wouldn't work but I think 
it's reasonable to expect for such device to be flexible about cacheline 
config.

> > Oh yeah, that's what I was trying to say, and I don't want to go down 
> > that route.  So, I guess this one is settled.
>
> hrm...if the driver can put a safe value in cachelinesize register
> and NOT enable MWI, I can imagine a significant performance boost
> if the device can use MRM or MRL. But IMHO it's up to the driver
> writers (or other contributors) to figure that out.
>
> Current API (pci_set_mwi()) ties enabling MRM/MRL with enabling MWI
> and I don't see a really good reason for that. Only the converse
> is true - enabling MWI requires setting cachelinesize.

arch/i386/pci/common.c overrides cacheline size to min 32 regardless of 
actual size.  So, we seem to be using larger cacheline size for MWI already.

Jeff pointed out that there actually are devices which limit CLS config. 
 IMHO, making PCI configure CLS automatically and provide helpers to 
LLD to override it if necessary should cut it.

Thanks.

--
tejun
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