Alan Cox wrote:
Ar Gwe, 2006-08-11 am 12:08 +0100, ysgrifennodd Chris Pringle:
Unlikely as it would affect both. More likely would be that the ISA bus
clock is generated off the PCI bus clock and you have one of the
multipliers wrong or too high for the board.
Thats interesting, but wouldn't this produce strange side affects for
the 2.4 kernel as well? 2.4 works fine on both VIAs and Celerons.
That I wonder about. The power management stuff and some other things
that matter for timing are different however.
We don't use any kind of power management (not compiled in) as our
systems are always on... Is there any timing related options in the
kernel config you'd recommend I look at?
I'll give the interrupt disabling a go...
Its just a guess but if you have low latency stuff, you have pre-empt
enabled and you actually depend upon the semantics of inb_p/outb_p
giving delays reliably then I'm not convinced are guarantees are strong
enough
Specifically we don't have any pre-empt protection between the I/O delay
and the I/O so we could violate it as we don't have pre-empt disables in
inb_p/outb_p and if your CPU context switch is quick enough it could
trigger a problem.
Alan
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Okay, I've tried disabling both preemption and interrupts (separately,
and together) and its still hanging...
I've had the Celeron systems being thrashed for well over 4 days now,
and they are working fine... Why would the VIA system be any different?
They have a slightly different CPU speed (the VIAs are 1000MHz, whereas
the Celerons are 850MHz), but I would expect them to be fully compatible
otherwise... unless its a microcode bug?
Any more ideas? Do you think writing to port 0x80 could be causing issues?
Thanks,
Chris
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Chris Pringle
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