Ar Gwe, 2006-08-11 am 12:08 +0100, ysgrifennodd Chris Pringle:
> > Unlikely as it would affect both. More likely would be that the ISA bus
> > clock is generated off the PCI bus clock and you have one of the
> > multipliers wrong or too high for the board.
> >
> Thats interesting, but wouldn't this produce strange side affects for
> the 2.4 kernel as well? 2.4 works fine on both VIAs and Celerons.
That I wonder about. The power management stuff and some other things
that matter for timing are different however.
> I'll give the interrupt disabling a go...
Its just a guess but if you have low latency stuff, you have pre-empt
enabled and you actually depend upon the semantics of inb_p/outb_p
giving delays reliably then I'm not convinced are guarantees are strong
enough
Specifically we don't have any pre-empt protection between the I/O delay
and the I/O so we could violate it as we don't have pre-empt disables in
inb_p/outb_p and if your CPU context switch is quick enough it could
trigger a problem.
Alan
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