On Tue, 30 May 2006, Guennadi Liakhovetski wrote:
> On Tue, 30 May 2006, Tejun Heo wrote:
>
> > Nicolas Pitre wrote:
> > > I do have hardware that exhibits the problem and therefore I wish the
> > > discussion could be resumed.
>
> Partly to add myself to the cc-list, partly to add some oil in the fire -
> there have been a few discussions on arm-kernel recently, one of them
>
> http://marc.theaimsgroup.com/?t=114136178100001&r=1&w=2
>
> where at least you can get some more test results / failure pictures.
> However, many have also stated that the patch set from Tejun,
> unfortunately, doesn't fix 100% of IDE PIO cache coherency problems on
> ARM.
The other problem is probably due to a mistake in the interpretation of
some XScale document and if so is easily fixable (actually one bit
difference in the page table).
The much more fundamental issue of having dirty lines after PIO in a
VIVT cache that user space fails to see is a real and generic design
issue on its own.
Nicolas
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