RE: [PATCH] i386: PAE entries must have their low word cleared first

["Brunner, Richard" <Richard.Brunner@amd.com>]

> -----Original Message-----
> [mailto:linux-kernel-owner@vger.kernel.org] On Behalf Of 

> Nick Piggin wrote
> 
> Keir Fraser wrote:
> > 
> > [snip]
> > 
> > In more detail the problem is that, since we're still running on the 
> > page tables while clearing them, the CPU may choose to prefetch a 
> > half-cleared pte into its TLB, and then execute speculative memory 
> > accesses based on that mapping (including ones that may write-allocate 
> > cachelines, leading to problems like the AMD AGP GART deadlock Linux had 
> > a year or so back).
> 
> What do you mean, you're still running on the page tables? The CPU can
> still walk the pagetables?
> 
> Because if ptep_get_and_clear_full is passed non zero in the full
> argument, then that specific translation should never see another
> access. I didn't know CPUs now actually resolve TLB misses as part of
> speculative prefetching... does this really happen?

Yes, on AMD processors, speculative execution is allowed to install TLB translations. Assuming you are not in 64-bit mode, and can not use
mmx or sse instructions to zero out the naturally aligned 64-bit pte,
then what is being suggested makes sense: clear out the valid bit
first by writing the low 32-bits. No invalid translations are ever 
installed in the TLB.


> Do you have a pointer to where the AMD AGP GART deadlock was 
> discussed? Google is having some trouble finding it.

http://marc.theaimsgroup.com/?l=linux-kernel&m=102376926732464&w=2


> > The barrier is needed to ensure that the bottom half is  cleared before 
> > the top half. In fact it probably ought to be wmb() -- 
> that's clearer in intent and actually reduces to barrier() on all PAE capable platforms.

Maybe the barrier is needed for other architectures, but two writes
to WB memory are not going to happen out of order and so no
barrier is needed on x86 to the best of my knowledge.
 

	-Rich Brunner, AMD


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