RE: Problems with EDAC coexisting with BIOS

["Ong, Soo Keong" <soo.keong.ong@intel.com>]

To me, periodical is not a good design for error handling, it wastes
transaction bandwidth that should be used for other more productive
purposes.

It is more appropriate to have single handler, either OS or BIOS.

In general, the errors handler connect the errors to the interrupt or
interrutps. The handler should undhide (if it s hideable) the error
controller and read its registers upon interrupt, then carry out
appropriate actions to handle the erros.


-----Original Message-----
From: Alan Cox [mailto:alan@lxorguk.ukuu.org.uk] 
Sent: Monday, April 24, 2006 10:14 PM
To: Ong, Soo Keong
Cc: Gross, Mark; bluesmoke-devel@lists.sourceforge.net; LKML; Carbonari,
Steven; Wang, Zhenyu Z
Subject: RE: Problems with EDAC coexisting with BIOS

On Llu, 2006-04-24 at 21:59 +0800, Ong, Soo Keong wrote:
> Alan,
> 
> Have you understood how the errors are connected to the interrupts
> (either SMI, NMI, SCI)?

I believe so

> When does EDAC read the error status? Periodical or upon interrpt by
> errors?

Periodically currently. The sf development tree has some code for
handling the NMI case but this isn't actually useful because an NMI can
occur half way through a PCI config transaction.

Alan
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