On Llu, 2006-04-24 at 21:59 +0800, Ong, Soo Keong wrote:
> Alan,
>
> Have you understood how the errors are connected to the interrupts
> (either SMI, NMI, SCI)?
I believe so
> When does EDAC read the error status? Periodical or upon interrpt by
> errors?
Periodically currently. The sf development tree has some code for
handling the NMI case but this isn't actually useful because an NMI can
occur half way through a PCI config transaction.
Alan
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