RE: Synchronizing Bit operations V2

["Chen, Kenneth W" <kenneth.w.chen@intel.com>]

Christoph Lameter wrote on Thursday, March 30, 2006 7:02 PM
> We are talking about IA64 and IA64 only generates an single instruction 
> with either release or acquire semantics for the case in which either 
> smb_mb__before/after_clear_bit does nothing.
> 
> Neither acquire nor release is a memory barrier on IA64.


The use of
        smp_mb__before_clear_bit();
        clear_bit( ... );

is: all memory operations before this call will be visible before
the clear_bit().  To me, that's release semantics.

On ia64, we map the following:
#define Smp_mb__before_clear_bit      do { } while (0)
#define clear_bit                     clear_bit_mode(..., RELEASE)

Which looked perfect fine to me.  I don't understand why you say it does
not provide memory ordering.

- Ken
-
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/