On Thu, Mar 09, 2006 at 01:11:47AM +0300, Ivan Kokshaysky wrote:
> On Wed, Mar 08, 2006 at 01:57:34PM -0800, [email protected] wrote:
> > > Otherwise we have plenty of MMIO space.
> >
> > Not true. Plenty of root bridges have the same base/limit style
> > configuration registers, but they are non-standard. Even worse - the MMIO
> > hole thatthe chipset carves out, is not guaranteed to be big enough for
> > some new random allocation.
>
> I'm intrigued. Care to give us an example of such system (where the
> root bridge window is too small), please? lspci -vxxx?
I have systems where the BIOS sets up the IO hole to be the size of the
BARs it finds at PCI enum time. If I have a device that has a hidden BAR,
the hole won't cover it. Period.
> > Cleaning up and re-doing are not the same thing. The plethora of x86
> > chipsets makes this unpleasant at best and more likely unworkable.
>
> Yes, re-doing is a LOT simpler. ;-)
> If needed, we could introduce 'pci=totallyingnorefsckingbiossettings'
> boot option - it would be 10 or less lines of code.
Except for that whole chipset code thing. Have you dealt with the
fugliness that is the chipset? You're really glossing over it.
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