On Thu, Mar 09, 2006 at 12:21:53AM +0300, Ivan Kokshaysky wrote:
> On Wed, Mar 08, 2006 at 08:40:42AM -0800, [email protected] wrote:
> > Assigned from what pool? BIOS most likely sizes the hole to be a pretty
> > tight fit for all the resources it knows about. If there is suddenly a
> > new resource, you're in trouble.
>
> This can only be true when device in question is behind a pci-to-pci
> bridge (which is obviously not the case for ICH controllers you mentioned).
> Otherwise we have plenty of MMIO space.
Not true. Plenty of root bridges have the same base/limit style
configuration registers, but they are non-standard. Even worse - the MMIO
hole thatthe chipset carves out, is not guaranteed to be big enough for
some new random allocation.
> > We could teach linux about chipsets and let Linux re-do the whole
> > PCI-allocation process. But that's not an easy task, and is probably a
> > contentious idea.
>
> Linux knows how to do this for years. Actually, this is the way how alpha
> and some other platforms work. Since 2.6.13, this pretty much applies to
> x86 as well (we do respect BIOS PCI allocations, but we clean the things
> up after BIOS quite aggressively - see pci_assign_unassigned_resources() call).
Cleaning up and re-doing are not the same thing. The plethora of x86
chipsets makes this unpleasant at best and more likely unworkable.
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