On Fri, Feb 24, 2006 at 10:04:23AM -0500, Alan Stern wrote:
> What do you think of the two suggestions in my previous message?
Even if the read version of the lock only touches a cacheline local to
the cpu, you'd still have to use the lock prefix to allow for correctness
when a writer comes along. It is not cacheline bouncing that worries me,
it is serialising instructions and memory barriers as those hurt immensely
when the data is in the cache. I've been looking at a lot of profiles on
P4s of late, and every single locked instruction is painful as it means
all of the memory ordering rules come into play. Neither suggestion
addresses that overhead that has been introduced.
-ben
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