[PATCH 2/2] [x86] align per-cpu section to configured cache bytes

[Zach Brown <zach.brown@oracle.com>]

[x86] align per-cpu section to configured cache bytes

This matches the fix for a bug seen on x86-64.  Test booted on old hardware
that had 32 byte cachelines to begin with.

  Signed-off-by: Zach Brown <zach.brown@oracle.com>
---

 arch/i386/kernel/vmlinux.lds.S |    3 ++-
 1 files changed, 2 insertions(+), 1 deletion(-)

Index: 2.6.16-rc1-per-cpu-align/arch/i386/kernel/vmlinux.lds.S
===================================================================
--- 2.6.16-rc1-per-cpu-align.orig/arch/i386/kernel/vmlinux.lds.S	2006-01-27 13:21:34.000000000 -0800
+++ 2.6.16-rc1-per-cpu-align/arch/i386/kernel/vmlinux.lds.S	2006-01-27 13:32:55.000000000 -0800
@@ -7,6 +7,7 @@
 #include <asm-generic/vmlinux.lds.h>
 #include <asm/thread_info.h>
 #include <asm/page.h>
+#include <asm/cache.h>
 
 OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386")
 OUTPUT_ARCH(i386)
@@ -115,7 +116,7 @@
   __initramfs_start = .;
   .init.ramfs : AT(ADDR(.init.ramfs) - LOAD_OFFSET) { *(.init.ramfs) }
   __initramfs_end = .;
-  . = ALIGN(32);
+  . = ALIGN(L1_CACHE_BYTES);
   __per_cpu_start = .;
   .data.percpu  : AT(ADDR(.data.percpu) - LOAD_OFFSET) { *(.data.percpu) }
   __per_cpu_end = .;
-
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