On Tue, Jan 17, 2006 at 02:40:10PM -0500, John Richard Moser wrote: > Well, pages are typically 4KiB seen by the MMU. If you fault across > them, you need to have them cached in the TLB; if the TLB runs out of > room, you invalidate entries; then when you hit entries not in the TLB, > the TLB has to searhc for the page mapping in the PTE chain. > > There are 4MiB pages, called "huge pages," that if you clump 1024 > contiguous 4KiB pages together and draw a PTE entry up for can correlate > to a single TLB entry. In this way, there's no page faulting until you > cross boundaries spaced 4MiB apart from eachother, and you use 1 TLB > entry where you would normally use 1024. > Transparent superpages would certainly be nice. There's already various superpage implementations floating around, but not without their drawbacks. You might consider the Shimizu superpage patch for x86 if you're not too concerned about demotion when trying to swap out the page. There's some links on this subject on the ia64 wiki: http://www.gelato.unsw.edu.au/IA64wiki/SuperPages Alternately, if you're simply interested in cutting down on the page fault overhead and want a simpler and more naive approach, read the rice paper and consider something like the IRIX/HP-UX approach (though for x86, arm, etc. this might be slightly more work, since the larger pages are at the PMD level, as opposed to other architectures where it's just a matter of setting some bits in the PTE). Since this topic seems to come up rather frequently, perhaps it would be worthwhile documenting some of this on the linux-mm wiki.
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