Re: Dual core Athlons and unsynced TSCs

[Zan Lynx <zlynx@acm.org>]

On Fri, 2006-01-13 at 17:04 -0800, David Lang wrote: 
> On Sat, 14 Jan 2006, Andreas Steinmetz wrote:
> 
> > David Lang wrote:
> > Well, wait until there's AMD based dual core x86_64 laptops out there
> > (this email being written on a single core x86_64 one). I can already
> > see the faces of the unhappy future owners being told "use idle=poll"
> > when on battery and anyway going deaf by fan noise.
> >
> > (/me ducks and runs)
> 
> I'm not saying it's the right answer, but it's one of two workarounds 
> currently available.
> 
> idle=poll causes increased power useage
> 
> timer source change (mentioned earlier in this thread) limits timer 
> precision
> 
> neither of these are fixes, but by understanding the different costs 
> people can choose the work around they want to use while waiting for a 
> better fix.

A laptop user could also bind a process to a single CPU, and use the
scaling min/max values to lock CPU speed to a single value.  The TSC may
still stop during HLT, but software must be handling that already.

Wouldn't that provide an accurate TSC?
-- 
Zan Lynx <zlynx@acm.org>

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