Hi,
> Side note, why can't powerpc use lwsync for smp_wmb? The only problem seems
> to be that it allows loads to be reordered before stores, but that's
> OK with smp_wmb, right?
lwsync implies more ordering than eieio and so may take longer. lwsync
orders everything except store - load, and eieio just orders store - store.
On power3 an lwsync is a full sync which takes forever, although in
newer chips both lwsync and eieio tend to take the same number of
cycles.
> And why is smp_wmb() (ie. the non I/O barrier) doing eieio, while wmb() does
> not? And rmb() does lwsync, which apparently does not order IO at all...
Because people love to abuse the barrier macros :) grep for wmb in
drivers/net and look for the number of places wmb() is being used to
order memory and IO. Architecturally eieio is a store - store ordering
for IO and memory but not between the two. sync is slow but does
guarantee this.
SGIs mmiowb() might be useful for some of these cases but every time its
brought up everyone ends up confused as to its real use.
Really we should have io_*mb() and smp_*mb(). At that stage we may even
be able to kill the base *mb() macros.
Anton
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