Re: [patch 0/9] mutex subsystem, -V4

[Russell King <rmk+lkml@arm.linux.org.uk>]

On Thu, Dec 22, 2005 at 05:44:15PM +0100, Ingo Molnar wrote:
> * Nicolas Pitre <nico@cam.org> wrote:
> > > i'm curious, how would this ARMv6 solution look like, and what would be 
> > > the advantages over the atomic swap based variant?
> > 
> > On ARMv6 (which can be SMP) the atomic swap instruction is much more 
> > costly than on former ARM versions.  It however has ll/sc instructions 
> > which allows it to implement a true atomic decrement, and the lock 
> > fast path would look like: [...]
> 
> but couldnt you implement atomic_dec_return() with the ll/sc 
> instructions? Something like:
> 
> repeat:
>        ldrex   r1, [r0]
>        sub     r1, r1, #1
>        strex   r2, r1, [r0]
>        orrs    r0, r2, r1
>        jneq    repeat
> 
> (shot-in-the-dark guess at ARMv6 assembly)

atomic_dec_return() would be:

1:	ldrex	r1, [r0]
	sub	r1, r1, #1
	strex	r2, r1, [r0]
	teq	r2, #0
	bne	1b
	@ result in r1

But that's not really the main point Nico's making.  Yes, on ARMv6
there is little difference.  However, ARMv6 is _not_ mainstream yet.
The previous generation which do not have this is currently mainstream.

When it comes down to it, unlike x86 land where new CPU features are
taken up very quickly, the take up of new features on ARM CPUs is
a lot slower - it's a matter of years not a matter of months.
Therefore, we can expect ARMv5 architecture CPUs to be mainstream
at least for the next year or two, and these are the ones which
we should optimise for.

Nico's point still stands though - and I'd like to ask a more direct
question.  There is an efficient implementation for ARMv5 CPUs which
it appears we're being denied the ability to use.

Given that this has been argued for using clear technical arguments
over the last two days, I have yet to see any explaination why you're
choosing to ignore it.  Could you please explain why?

-- 
Russell King
 Linux kernel    2.6 ARM Linux   - http://www.arm.linux.org.uk/
 maintainer of:  2.6 Serial core
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