Re: [PATCH 1/12]: MUTEX: Implement mutexes

[Nicolas Pitre <nico@cam.org>]

On Sun, 18 Dec 2005, Alan Cox wrote:

> On Sad, 2005-12-17 at 20:29 -0500, Nicolas Pitre wrote:
> > out there.  The other 99% of actual ARM processors in the field only 
> > have the atomic swap (swp) instruction which is insufficient for 
> > implementing a counting semaphore (we therefore have to disable 
> > interrupts, do the semaphore update and enable interrupts again which is 
> > much slower than a swp-based mutex).
> 
> There are other approaches depending on how your CPU behaves and the
> probability of splitting an "atomic operation" including checking the
> return address range in the IRQ handler and ifs its in the 'atomic ops'
> page jumping to a recovery function. If you are sneaky in how you lay
> out your virtual address space it becomes a single unconditional or on
> kernel->kernel interrupt returns.

Well we sort of do something similar to implement cmpxchg for NPTL usage 
from user space (forcing the abortion of the operation if an interrupt 
happens in the middle of it).  But it's more hassle to do in kernel 
space.


Nicolas
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