On Sad, 2005-12-17 at 20:29 -0500, Nicolas Pitre wrote:
> out there. The other 99% of actual ARM processors in the field only
> have the atomic swap (swp) instruction which is insufficient for
> implementing a counting semaphore (we therefore have to disable
> interrupts, do the semaphore update and enable interrupts again which is
> much slower than a swp-based mutex).
There are other approaches depending on how your CPU behaves and the
probability of splitting an "atomic operation" including checking the
return address range in the IRQ handler and ifs its in the 'atomic ops'
page jumping to a recovery function. If you are sneaky in how you lay
out your virtual address space it becomes a single unconditional or on
kernel->kernel interrupt returns.
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