Linh Dang wrote:
Do you now see what I mean? (yup, ARM is a llsc architecture.)Well, it may be true for ARM but for ppc (i dunno what exactly llsc means but someone in the thread put ppc in llsc group) it's:
load locked or load with lock, IIRC.
loop:
load-reserve foo => old
new = old * N
store-conditional new => foo
if failed goto loop
The point is that the typical use case for a cmpxchg is less optimal if cmpxchg is simulated with llsc than if the same functionality were directly implemented with llsc instructions. -- SUSE Labs, Novell Inc.Send instant messages to your online friends http://au.messenger.yahoo.com -
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