Re: [RFC 3/6] Make nr_pagecache a per zone counter

[Marcelo Tosatti <marcelo.tosatti@cyclades.com>]

On Sun, Dec 11, 2005 at 08:48:40PM +0100, Andi Kleen wrote:
> > By the way, why does nr_pagecache needs to be an atomic variable on UP systems?
> 
> At least on X86 UP atomic doesn't use the LOCK prefix and is thus quite
> cheap. I would expect other architectures who care about UP performance
> (= not IA64) to be similar.

But in practice the variable does not need to be an atomic type for UP, but
simply a word, since stores are atomic on UP systems, no?

Several arches seem to use additional atomicity instructions on 
atomic functions:

PPC:
static __inline__ void atomic_add(int a, atomic_t *v)
{
        int t;

        __asm__ __volatile__(
"1:     lwarx   %0,0,%3         # atomic_add\n\
        add     %0,%2,%0\n"
        PPC405_ERR77(0,%3)
"       stwcx.  %0,0,%3 \n\
        bne-    1b"
        : "=&r" (t), "=m" (v->counter)
        : "r" (a), "r" (&v->counter), "m" (v->counter)
        : "cc");
}

"lwarx" and "stwcx." wouldnt be necessary for updating nr_pagecache 
on UP.


SPARC:
int __atomic_add_return(int i, atomic_t *v)
{
        int ret;
        unsigned long flags;
        spin_lock_irqsave(ATOMIC_HASH(v), flags);

        ret = (v->counter += i);

        spin_unlock_irqrestore(ATOMIC_HASH(v), flags);
        return ret;
}



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