* George Anzinger <[email protected]> wrote:
> > yeah, and that's an assumption that simplifies things on SMP
> > significantly. PIT on SMP systems for HRT is so gross that it's not
> > funny. If anyone wants to revive that notion, please do a separate
> > patch and make the case convincing enough ...
>
> Lets not talk about PIT, but, a lot of SMP platforms do NOT have per
> cpu timers. For those, it would seem having per cpu lists to handle
> the timer is not really reasonable.
frankly, such systems are rare, and are an afterthought at most. Think
about it: 8 CPUs and only one hres timer source? It cannot work nor
scale well.
i agree that they might eventually be handled (although i think we
shouldnt bother, all sane SMP designs have per-CPU timers), but we
definite wont design for them. What such an architecture has to do is to
provide the proper do_hr_timer_int() and arch_hrtimer_reprogram()
semantics, via locking around that timer source (naturally), and via
cross-CPU calls - as if they were per-CPU timers.
Ingo
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