Re: [PATCH 04/11] hpt366: write the full 4 bytes of ROM address, not just low 1 byte

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didn't Linus find similar bugs in a couple of the other hpt drivers as well? if so can they be fixed at the same time?

David Lang

On Wed, 14 Sep 2005, Chris Wright wrote:

Date: Wed, 14 Sep 2005 18:03:47 -0700
From: Chris Wright <[email protected]>
To: [email protected], [email protected]
Cc: Justin Forbes <[email protected]>,
    Zwane Mwaikambo <[email protected]>, Theodore Ts'o <[email protected]>,
    Randy Dunlap <[email protected]>,
    Chuck Wolber <[email protected]>, [email protected], [email protected],
    [email protected], Linus Torvalds <[email protected]>,
    Chris Wright <[email protected]>
Subject: [PATCH 04/11] hpt366: write the full 4 bytes of ROM address,
    not just low 1 byte

-stable review patch.  If anyone has any objections, please let us know.
------------------

This is one heck of a confused driver.  It uses a byte write to a dword
register to enable a ROM resource that it doesn't even seem to be using.

"Lost and wandering in the desert of confusion"

Signed-off-by: Linus Torvalds <[email protected]>
Signed-off-by: Chris Wright <[email protected]>
---
drivers/ide/pci/hpt366.c |    8 ++++++--
1 files changed, 6 insertions(+), 2 deletions(-)

Index: linux-2.6.13.y/drivers/ide/pci/hpt366.c
===================================================================
--- linux-2.6.13.y.orig/drivers/ide/pci/hpt366.c
+++ linux-2.6.13.y/drivers/ide/pci/hpt366.c
@@ -1334,9 +1334,13 @@ static int __devinit init_hpt366(struct
static unsigned int __devinit init_chipset_hpt366(struct pci_dev *dev, const char *name)
{
	int ret = 0;
-	/* FIXME: Not portable */
+
+	/*
+	 * FIXME: Not portable. Also, why do we enable the ROM in the first place?
+	 * We don't seem to be using it.
+	 */
	if (dev->resource[PCI_ROM_RESOURCE].start)
-		pci_write_config_byte(dev, PCI_ROM_ADDRESS,
+		pci_write_config_dword(dev, PCI_ROM_ADDRESS,
			dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);

	pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));

--
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