Mikael Pettersson <[email protected]> writes:
> Andi Kleen writes:
> > On Tuesday 30 August 2005 16:45, Alan Cox wrote:
> > > On Llu, 2005-08-29 at 18:20 -0600, Eric W. Biederman wrote:
> > > > ways. Currently this code only allows for an additional flavor
> > > > of uncached access to physical memory addresses which should be hard
> > > > to abuse, and should raise no additional aliasing problems. No
> > > > attempt has been made to fix theoretical aliasing problems.
> > >
> > > Even an uncached/cached alias causes random memory corruption or an MCE
> > > on x86 systems. In fact it can occur even for an alias not in theory
> > > touched by the CPU if it happens to prefetch into or speculate the
> > > address.
> > >
> > > Also be sure to read the PII Xeon errata - early PAT has a bug or two.
> >
> >
> > We can always force cpu_has_pat == 0 on these machines.
> > I don't think it is worth it to add any more complicated workarounds
> > for old broken systems.
>
> I don't have the spec updates in front of me, but I believe the PAT
> bug existed well into the P4 line. The workaround is simply to make
> the high 4 PAT entries identical to the low 4 entries. (But I confess
> to not having a clue as to whether it's still useful then or not.)
It is still useful even if that is the case. Unless we need something
more than WC we don't have a need for anything else.
If you could track down the reference you are thinking of I would
appreciate it. According to the errata I can find simply not using
the high 4 entries is sufficient, to avoid the problem.
Eric
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