Re: [PATCH] enhance x86 MTRR handling

[David Addison <addy@quadrics.com>]

Dave Jones wrote:
> Whilst your changes may have merit, I'd much rather see effort spent
> on getting PAT into shape than further massaging MTRR.  Its well past its
> smell-by-date, and theres been no activity whatsoever afaik on getting
> Terrence Ripperda's cachemap stuff beaten into shape.
>
> I'll dust off the last version he sent and diff against latest-mm later
> so it can get some more commentary. It seems everyone is in violent
> agreement that we want PAT support, but nothing seems to happen.
Yes we tried to contact the cachemap author but just found dead email
addresses, so in the end we switched to using PAT.
But rather that make kernel changes, we simply wrote a startup utility to
program the MSR registers using /dev/cpu/%d/msr
Our device driver then reads the IA32CR_PAT MSR and looks for a write-combining
entry (value 0x01) and uses the slot # to program the correct PTE bits.

But having a default write-combining MSR slot and a defined call to enable it
would be good; I believe Hugo Kohmann from Dolphin has a patch to do this for
x86_64 at least.

Cheers
Addy.

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