Re: [PATCH] enhance x86 MTRR handling

[Dave Jones <davej@redhat.com>]

On Thu, May 12, 2005 at 11:08:21AM +0200, Jan Beulich wrote:

 > - the code to correct inconsistent settings during secondary processor
 >   startup tried (if necessary) to correct, among other things, the value
 >   in IA32_MTRR_DEF_TYPE, however the newly compute value would never get
 >   used to be stored in the respective MSR
 > - the generic range validation code checked that the end of the
 >   to-be-added range would be above 1MB; the value checked should have been
 >   the start of the range
 > - when contained regions are detected, previously this was allowed only
 >   when the old region was uncacheable; this can be symmetric (i.e. the new
 >   region can also be uncacheable) and even further as per Intel's
 >   documentation write-trough and write-back for either region is also
 >   compatible with the respective opposite in the other

Whilst your changes may have merit, I'd much rather see effort spent
on getting PAT into shape than further massaging MTRR.  Its well past its
smell-by-date, and theres been no activity whatsoever afaik on getting
Terrence Ripperda's cachemap stuff beaten into shape.

I'll dust off the last version he sent and diff against latest-mm later
so it can get some more commentary. It seems everyone is in violent
agreement that we want PAT support, but nothing seems to happen.

		Dave

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