On Fri, 08 Apr 2005 09:19:39 +0400
Evgeniy Polyakov <[email protected]> wrote:
> > I know, the same thing holds for most architectures, including i386.
> > However, this is not an issue for uni-processor kernels anywhere else,
> > so what's so special about MIPS?
>
> Does i386 or ppc has cached and uncached memory?
Yes, they do.
> No, i386, ppc and others do not require sync on uncached memory access,
> and only instruction not data cache sync on SMP.
On MIPS, all the MIPS atomic operations will operate on cached memory.
And as far as a uniprocessor cpu is concerned, updating the cache is
all that matters.
In fact, this SYNC instruction seems unnecessary even on SMP. If the
cache is updated, it is part of the coherent memory space and thus
MOESI main bus SMP cache coherency transactions will see the update
value. When another processor does a "read-to-share" or "read-to-own"
request on the main bus, the processor which did the atomic OP will
provide the correct data from it's cache in response to that transaction.
So what you have to do is show me an example where the MIPS kernel can
do an atomic.h operation on uncached memory. I even think that is
invalid, come to think of it.
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