I heard from Larry Walton who was apparently seeing this problem as
well. He tried my recent "sata_nv: cleanup ADMA error handling v2" patch
and originally thought it fixed the problem, but it turned out to only
make it happen less often.
I wouldn't expect that patch to have an effect on this problem. If it
seems to reduce the frequency that would tend to be further evidence of
some kind of timing-related issue where the code change just happens
to make a difference.
I'll see if I can come up with a debug patch for people having this
problem to try, which prints out when a flush command is issued and what
interrupts happen when a flush is pending.
There is one important difference between ADMA and non-ADMA mode for
non-DMA commands like flushes, which didn't come to mind before: ADMA
mode uses MMIO registers on the controller whereas non-ADMA mode uses
legacy IO registers. Posted write flushing is a concern with MMIO
registers but not with PIO, the libata core is supposed to handle this
but maybe it doesn't in some case(s). In fact, just looking at
libata-sff.c there's this comment on the ata_exec_command_mmio function:
* FIXME: missing write posting for 400nS delay enforcement
That seems a bit suspicious..
--
Robert Hancock Saskatoon, SK, Canada
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Home Page: http://www.roberthancock.com/
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