Thanks David; > Somewhat off topic for this list .. Yes I agree somewhat, but a couple of years ago I asked if this kind of question was acceptable on the Fedora users list. From time to time, I have had questions that touch on the physical layer of my computer. I have no interest in becoming an Engineer. If I ask on more technical sites (I have tried) I either get answers that are so technical, they are no answers at all -- for my purposes, or, people get aggravated at such basic questions and feel that I am wasting their time. On the other hand, on the Fedora list there are some people who like to take a shot (like you just did) but can keep the answers at my level. Some people have indicated the same interest or a passing curiosity, that I have on how these things work. I try to indicate in the Heading the type of question I am asking so that those who want to skip the question can. > > I have no expertise in this but out of curiousity I had a look at the > datasheet. My conclusions are below. > No doubt there will be others here with greater expertise who are > welcome to correct any errors. > > Reference: http://download.intel.com/design/processor/datashts/318732.pdf > > The intent of the datasheet is to describes its interfaces, not its > internal operation. > > 1) Table 2: the processor outputs a byte that controls the regulator > to provide it a supply voltage VCC in the range 0.5 to 1.6 V. > > 2) Table 4 Note 7: VTT is the databus (frontside bus FSB) fixed > reference voltage. It does not vary. > > 3) Table 3: VTT absmax = 1.45V > > 4) Table 4: VTT typical = 1.2V > > 5) Section 2.7: The databus uses GTL+. The "0 or 1" reference > threshold for input voltages is GTLREF which is derived from VTT by a > simple resistive divider. > > 6) Table 15: With resistors 57.6 and 100 ohm: GTLREF=VTT*100/(57.6+100)=0.76V > > 7) So for the databus: > Table 11: (approx) 0 < VIL < GTLREF (VIL = voltage detected as 0 = > below 0.76V) > Table 11: (approx) GTLREF < VIH < VTT (VIH = voltage detected as 1 = > above 0.76V) > Table 11: (approx) VOH = VTT (VOH = voltage output for 1 = 1.2V) > I could not see any VOL (voltage output for 0) for the FSB in this datasheet. > > 8) Table 12 and Table 13 specify open-drain and cmos interfaces which > use different voltages. > > Background docs: > http://en.wikipedia.org/wiki/Gunning_Transceiver_Logic > http://focus.ti.com/lit/an/scea003a/scea003a.pdf (mentions VOL < 0.4V for GTL+) > > Hope this is useful. Yes, it was very useful. It gave me the Gunning_Transceiver_Logic as the appropriate search criteria for what I wanted to know. This site seems to cover it: http://encyclopedia2.thefreedictionary.com/Gunning+Transceiver+Logic "Gunning Transceiver Logic - (GTL) A standard for electrical signals in CMOS circuits used to provide higher data transfer speeds with smaller voltage swings The GTL signal swings between 0.4 volts and 1.2 volts with a reference voltage of about 0.8 volts. Only a small deviation of 0.4 volts (or thereabouts) from the reference voltage is required to switch between on and off states. Therefore, a GTL signal is said to be a low voltage swing logic signal. Gunning Transceiver Logic has several advantages. The resistive termination of a GTL signal provides a clean signalling environment Moreover, the low terminating voltage of 1.2 volts results in reduced voltage drops across the resistive elements. GTL has low power dissipation and can operate at high frequency and causes less electromagnetic interference (EMI)." I am going to make the assumption that the voltages used on the FSB would be the same as are used by transistors inside the CPU and DRAM. Thanks again !! -- Regards Bill Fedora 11, Gnome 2.26.3 Evo.2.26.3, Emacs 23.1.1 -- fedora-list mailing list fedora-list@xxxxxxxxxx To unsubscribe: https://www.redhat.com/mailman/listinfo/fedora-list Guidelines: http://fedoraproject.org/wiki/Communicate/MailingListGuidelines
