Robert Hancock wrote:
The case of the device built into the K8 northbridge that's unreachable
by MMCONFIG kind of makes sense, since the northbridge is what's
translating the MMCONFIG memory access into config accesses. It seems
bizarre to me that a bridge chip could possibly have such a problem. The
MMCONFIG access should get translated into a configuration space access
in the northbridge and from that point on there's no difference between
an MMCONFIG and type1 access.
Robert's point is well taken.
Only northbridge chips can give us this kind of trouble, and the only
chips mentioned in the present discussion as not being mmconf-compliant
are northbridges (8132, ht1000).
The patch is aware of this, so once a root bus has been programmed for
legacy pci config access, all descendent buses automatically inherit
this access mechanism and are therefore not probed by the patch.
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