> Yes. It is that wonderful time of the year again.
> No, no. We are not talking about holiday season or new year here.
>
> We are talking about one another rehash of "why we do not support PAT in x86"
> question and series of patches that implement some PAT support before going
> into hibernation again. Only difference is that we hope to take this little
> further this time and may be really get this support into
> upstream kernel soon.
Woot, PAT support: this time we mean it!!
I'll just give one comment after a reading your todo..
> * Do we need to allow RAM pages to be mapped as WC? If not, then
> we don't need to follow the TLB flush mechanism (make pte not present,
> flush, and set pte with new mapping) mentioned in section 10.12.4 of SDM
> Vol3a.
Yes, the main use for GPUs is to have RAM pages mapped WC, and placed into
a GART on the GPU side, currently for Intel IGD we are okay as the CPU can
access the GPU GART aperture, but other chips exist where this isn't
possible, I think poulsbo and possible some of the AMD IGPs..
Dave.
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