>-----Original Message-----
>From: [email protected]
>[mailto:[email protected]] On Behalf Of Paul
>Rolland (???・???)
>Sent: Thursday, November 29, 2007 10:53 PM
>To: Pallipadi, Venkatesh
>Cc: Linux Kernel; Siddha, Suresh B; [email protected]
>Subject: Re: constant_tsc and TSC unstable
>
>Hello,
>
>On Thu, 29 Nov 2007 15:29:49 -0800
>"Pallipadi, Venkatesh" <[email protected]> wrote:
>
>
>
>> TSCs on Core 2 Duo are supposed to be in sync unless CPU
>supports deep idle
>> states like C2, C3. Can you send the full /proc/cpuinfo and
>full dmesg.
>>
>Sure I can...
>[root@tux log]# cat /proc/cpuinfo
>processor : 0
>vendor_id : GenuineIntel
>cpu family : 6
>model : 15
>model name : Intel(R) Core(TM)2 CPU T5300 @ 1.73GHz
>stepping : 2
>cpu MHz : 800.000
>cache size : 2048 KB
>physical id : 0
>siblings : 2
>core id : 0
>cpu cores : 2
>fdiv_bug : no
>hlt_bug : no
>f00f_bug : no
>coma_bug : no
>fpu : yes
>fpu_exception : yes
>cpuid level : 10
>wp : yes
>flags : fpu vme de pse tsc msr pae mce cx8 apic mtrr
>pge mca cmov pat ps
>e36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe nx lm
>constant_tsc arch_perfmo
>n pebs bts pni monitor ds_cpl est tm2 ssse3 cx16 xtpr lahf_lm
>bogomips : 3461.13
>clflush size : 64
>
Tried reproducing this here, but on a similar system (slightly newer CPU stepping) I don’t see this happening. This error does not matter on this particular system as even with TSC synchronization passes, TSC is going to be disabled later due to C2, C3 states, with a message like this
Marking TSC unstable due to: TSC halts in idle.
Will try to reproduce it on other systems to see whether there are any bugs in sync routines.
Thanks,
Venki
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