Andi Kleen wrote:
Are we putting the system back in PIC mode or virtual wire mode? I have
not seen systems which support PIC mode. All latest systems seems
to be having virtual wire mode. I think in case of PIC mode, interrupts
Yes it's probably virtual wire. For real PIC mode we would need really
old systems without APIC.
can be delivered to cpu0 only. In virt wire mode, one can program IOAPIC
to deliver interrupt to any of the cpus and that's what we have been
The code doesn't try to program anything specific, it just restores the state
that was left over originally by the BIOS.
So if the BIOS originally left the IOAPIC in a state where the timer
interrupts were only going to CPU0 then by restoring that state we could
be bringing this problem upon ourselves when we restore that state.
Would anyone have any problems with code that simply verified that the
state which we are restoring allowed interrupts to get to the processor
that we are currently crashing on and if not, poked in a reasonable value.
Yes this would add some complexity to the code paths where we were
crashing but it could prevent the problem that we are seeing. It seems
like a small fairly safe change rather than a big disruptive change like
moving the initialization of the IOAPIC earlier in the boot process.
-Andi
--
-ben
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