On Fri, 23 Nov 2007, Alan Cox wrote:
> Its usually faster if you don't misalign on x86 as well.
i'm not sure if i agree with "usually"... but i know you (alan) are
probably aware of the exact requirements of the hw.
for everyone else:
on intel x86 processors an access is unaligned only if it crosses a
cacheline boundary (64 bytes). otherwise it's aligned. the penalty for
crossing a cacheline boundary varies from ~12 cycles (core2) to many
dozens of cycles (p4).
on AMD x86 pre-family 10h the boundary is 8 bytes, and on fam 10h it's 16
bytes. the penalty is a mere 3 cycles if an access crosses the specified
boundary.
if you're making <= 4 byte accesses i recommend not worrying about
alignment on x86. it's pretty hard to beat the hardware support.
i curse all the RISC and embedded processor designers who pretend
unaligned accesses are something evil and to be avoided. in case you're
worried, MIPS patent 4,814,976 expired in december 2006 :)
-dean
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