Morrison, Tom wrote:
The plot thickens - it looks like it might be some type
of problem interacting with the setup of my 4Gig DDR memory
and how I setup some translation windows in my MPC8548E
I realized this morning that I have an inbound/ output PEX window
Translation Setup for mapping all from/to PEX bus to outside
the physical 4GIG memory space (i.e.: up at 0xC_xxxx_xxxx). Thus,
all output operations that translation from 0xC_xxxx_xxxx to
the pci 32 bit address of xxxx_xxxx) - and vice versa for for
the inbound. Note: we also have a straight 1:1 translation mapping
as well for the lower 4Gig - so that's why this worked without
the below mentioned change...
So, I changed the Request & Response Hi Addresses (which were
Being shifted by 32 bits down anyways) and 'OR' that with my
0xC (so the effective 64bit DMA address is 0xC_xxxx_xxxx (where
Xxxx_xxxx is the effective address). This was what we did to
solve the problem with the Marvel Linux driver that we got from
the Marvel site....
This all works just fine with ONLY 2 gig of memory in the system
(and still have these inbound/output pex translation windows),
but fails when I put back the 4 Gig (and the 8Gig) DDR memory.
Unfortunately, this still hasn't solved the problem though -
so there is something else which I am not seeing?
..
I don't know much about how 32-bit PPC deals with memory addresses
that are more than 32-bits..
But does this patch have any effect:
--- old/drivers/ata/sata_mv.c 2007-10-12 12:43:44.000000000 -0400
+++ linux/drivers/ata/sata_mv.c 2007-11-15 17:12:24.000000000 -0500
@@ -685,7 +685,7 @@
{
int rc;
- if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
+ if (0 && !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
if (rc) {
rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
-
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