Re: question on odd APIC behavior

[Oliver Neukum <oliver@neukum.org>]

Am Donnerstag 15 November 2007 schrieb Maciej W. Rozycki:
> On Thu, 15 Nov 2007, Oliver Neukum wrote:

> > I am seeing an interrupt for an UHCI on #20 CPU1 also arriving on
> > #19 CPU0, triggering the spurious interrupt detection.
> 
>  Well, if you see spurious interrupt detection triggered, then it is not a 
> problem with the interrupt being delivered multiple times (that's handled 
> silently by the interrupt dispatched), but likely the interrupt line being 
> deasserted too late.  Does it happen frequently?  If your ERR counter in 
> /proc/interrupts increments quite fast, then perhaps a driver does not 
> handle interrupts well enough for your system.  Or there is noise on an 
> interrupt line.
> 
>  You would have to provide more information to get more accurate feedback.

On irq 20, there's an UHCI, on irq 19 is an EHCI. For every interrupt on 20
there's a spurious interrupt on 19. USB devices on bus of the controller on 20
work. So I know all interrupts are seen. ERR does not increase. Interrupts
for devices on the bus of the controller on 19 arrive at 19 only.
As far as I can determine there are really interrupts on both CPUs on
different vectors for one physical interrupt request.

	Regards
		Oliver
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