Alan Cox <[email protected]> wrote:
> Ok so these are not addresses but magic registers in the processor ? Then
> I guess volatile makes complete sense.
They are such magic registers, though of various grades.
Some are part of the CPU core and affect things like CPU core itself, CPU
caches, MMU/TLB and exceptions/interrupts. Others are on-silicon devices such
as the serial ports, the bus controller, the SDRAM controller.
> For PIO (virtual DMA or otherwise) the locking does that. Because
> spin_unlock and spin_lock are compiler barriers the need to use volatile
> shouldn't normally be there. If you are doing it via asm without locks
> then I would expect atomic_t because the sematics of volatile are
> horribly vague on their own ?
Using memory barriers ought to be good enough for the ring buffer. There
aren't actually any atomic ops available other than bit-set and bit-clear.
David
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