Re: Quad core CPU detected but shows as single core in 2.6.23.1

[Peter Zijlstra <a.p.zijlstra@chello.nl>]

On Sun, 2007-11-04 at 19:52 +0100, Andi Kleen wrote:
> Chris Snook <csnook@redhat.com> writes:
> 
> >> Marking TSC unstable due to TSCs unsynchronized
> >
> > This is probably wrong.  The TSC is on the northbridge on Barcelona
> > chips, so every core on the die should be in sync.  Hypothetically you
> > could have different speed northbridges in different sockets, but
> > we've never tried very hard to support that case anyway.  We should
> > probably be marking the TSC as stable on Barcelona chips.
> 
> It's a little more complicated. Stable clock is only guaranteed as long 
> as the CPUs all run on the same clock crystal. That is true 
> when they're all on the current motherboard. But at least for K8
> there were several systems that consist of multiple motherboards
> and HT cables inbetween them (like all the 8 socket systems).
> On those the TSCs can drift too with Fam10h. I'm not aware
> of any of those shipping yet, but since it's essentially 
> the same platform as K8 they will appear sooner or later.
> 
> So far we lack a reliable way to detect this condition. If it could
> be detected it would be possible to switch to TSC timing
> for the single motherboard systems.

Would it not be as simple as looking at the BIOS provided topology
information? If nr sockets > 4 assume multiple board.

Of course one could run a multi board solution and not utilize all
sockets, in which case the heuristic would fail, but I guess buying such
an expensive solution and then not sticking in the cpus is rather rare.


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