On Thu, 2007-10-18 at 15:52 -0700, Linus Torvalds wrote:
>
> On Fri, 19 Oct 2007, Benjamin Herrenschmidt wrote:
> >
> > The barrier would guarantee that ioc->active (and in fact the write to
> > the chip too above) are globally visible
>
> No, it doesn't really guarantee that.
>
> The thing is, there is no such thing as "globally visible".
>
> There is a "ordering of visibility wrt CPU's", but it's not global, it's
> quite potentially per-CPU. So a barrier on one CPU doesn't guarantee
> anything at all without a barrier on the *other* CPU.
>
> That said, the interrupt handling itself contains various barriers on the
> CPU's that receive interrupts, thanks to the spinlocking. But I do agree
> with Herbert that adding a "smb_mb()" is certainly in no way "obviously
> correct", because it doesn't talk about what the other side does wrt
> barriers and that word in memory.
I agree and you can see that in fact, we don't have enough barrier on
the other side since spin_unlock doesn't prevent subsequent loads from
crossing a previous store...
I wonder if that's worth trying to address, adding a barrier in
handle_IRQ_event for example, or we can continue ignoring the barrier
and let some drivers do their own fixes in fancy ways.
Ben.
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