On Mon, Sep 10, 2007 at 02:36:26PM -0700, Christoph Lameter wrote:
> On Mon, 10 Sep 2007, Paul E. McKenney wrote:
>
> > The one exception to this being the case where process-level code is
> > communicating to an interrupt handler running on that same CPU -- on
> > all CPUs that I am aware of, a given CPU always sees its own writes
> > in order.
>
> Yes but that is due to the code path effectively continuing in the
> interrupt handler. The cpu makes sure that op codes being executed always
> see memory in a consistent way. The basic ordering problem with out of
> order writes is therefore coming from other processors concurrently
> executing code and holding variables in registers that are modified
> elsewhere. The only solution that I know of are one or the other form of
> barrier.
So we are agreed then -- volatile accesses may be of some assistance when
interacting with interrupt handlers running on the same CPU (presumably
when using per-CPU variables), but are generally useless when sharing
variables among CPUs. Correct?
Thanx, Paul
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