* Andi Kleen <[email protected]> wrote:
> > i know there are some incredibly broken (but rare) boxes where the bios
> > will report it only knows C1 and do C2? Is that the case you are
> > referring to, or is there something else too?
>
> There are first a couple of older and not so old (Centaur) chips that
> generally stop the TSC in C1.
there's not much we can do about them: the ACPI code doesnt measure
their idle time, right? This is mostly for statistics purposes, so
unless "broken" means tons of boxes, we dont have to have 100% coverage.
> And also some boxes who shouldn't have anything deeper than C2 have
> trouble with the TSC. For example I got a Opteron machine (which
> definitely shouldn't have any C2 since it's two socket) where the TSC
> appears to stop or at least slow down a lot in C1.
how much is "a lot" in C1? There's an AMD TSC-slows-down-C1 erratum but
that should be less than 1%. (which is fine enough for idle time
measurements)
> And thirdly it's just unclean to add all kinds of custom hooks there.
> It was already ugly in NOHZ, please don't continue that.
i'm not opposed to the idle notifiers but iirc the idle notifiers caused
problems in themselves so part of them were reverted. We can do this
more cleanly in .24 - it will make the benefits of the notifier cleanup
even more apparent.
Ingo
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