It seems unlikely, but access to self_id_cpu[0] could at least in theory
be deferred until after the loop over self_id_cpu[1..n] or even after
the subsequent reg_read. Enforce the desired order by a read barrier.
Also prevent the reg_read from being reordered relative to the for loop.
This isn't necessary if the loop's conditional printk counts as an
implicit barrier, but better make it explicit.
(self_id_cpu[] is a coherent DMA buffer.)
Signed-off-by: Stefan Richter <[email protected]>
---
drivers/firewire/fw-ohci.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
Index: linux/drivers/firewire/fw-ohci.c
===================================================================
--- linux.orig/drivers/firewire/fw-ohci.c
+++ linux/drivers/firewire/fw-ohci.c
@@ -30,6 +30,7 @@
#include <asm/uaccess.h>
#include <asm/semaphore.h>
+#include <asm/system.h>
#include "fw-transaction.h"
#include "fw-ohci.h"
@@ -926,6 +927,7 @@ static void bus_reset_tasklet(unsigned l
self_id_count = (reg_read(ohci, OHCI1394_SelfIDCount) >> 3) & 0x3ff;
generation = (le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff;
+ rmb();
for (i = 1, j = 0; j < self_id_count; i += 2, j++) {
if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1])
@@ -946,7 +948,7 @@ static void bus_reset_tasklet(unsigned l
* the two generations match we know we have a consistent set
* of self IDs.
*/
-
+ barrier();
new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff;
if (new_generation != generation) {
fw_notify("recursive bus reset detected, "
--
Stefan Richter
-=====-=-=== =--- =--=-
http://arcgraph.de/sr/
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