Altix supports "posted DMA", so that DMA may complete out
of order. In some cases it's necessary for a driver to
ensure that in-flight DMA has been flushed to memory for
correct operation.
In particular this can be a problem with Infiniband, where
writes to Completion Queues can race with DMA of data.
The following patchset addresses this problem by allowing a
memory region to be mapped with a "barrier" attribute. (On
Altix, writes to memory regions with the barrier attribute
have the side effect that in-flight DMA gets flushed to host
memory.)
There are three patches in this set:
[1/3] dma: introduce no-op stub "dma_flags_set_dmaflush"
[2/3] dma: override "dma_flags_set_dmaflush" for sn-ia64
[3/3] dma: use dma_flags_set_dmaflush in ib_umem_get
(mthca only, for now)
--
Arthur
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