On Tuesday 07 August 2007, Bryan Wu wrote:
> - /* Enable UART0 RX and TX on pin 7 & 8 of PORT E */
> - bfin_write_PORTE_FER(0x180 | bfin_read_PORTE_FER());
> - bfin_write_PORTE_MUX(0x3C000 | bfin_read_PORTE_MUX());
> + peripheral_request(P_UART0_TX, DRIVER_NAME);
> + peripheral_request(P_UART0_RX, DRIVER_NAME);
This is not a GPIO API, so the patch summary and description
are wrong. That's pin muxing. You didn't change any of
the GPIO related calls.
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