On Thu, 16 Aug 2007, Paul Mackerras wrote:
> Those barriers are for when we need ordering between atomic variables
> and other memory locations. An atomic variable by itself doesn't and
> shouldn't need any barriers for other CPUs to be able to see what's
> happening to it.
It does not need any barriers. As soon as one cpu acquires the
cacheline for write it will be invalidated in the caches of the others. So
the other cpu will have to refetch. No need for volatile.
The issue here may be that the compiler has fetched the atomic variable
earlier and put it into a register. However, that prefetching is limited
because it cannot cross functions calls etc. The only problem could be
loops where the compiler does not refetch the variable since it assumes
that it does not change and there are no function calls in the body of the
loop. But AFAIK these loops need cpu_relax and other measures anyways to
avoid bad effects from busy waiting.
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