Re: [patch 3/3] genirq: mark io_apic level interrupts to avoid resend

[Jarek Poplawski <jarkao2@o2.pl>]

On Mon, Aug 13, 2007 at 02:07:37PM -0500, Benjamin Herrenschmidt wrote:
> On Mon, 2007-08-13 at 15:53 +0200, Jarek Poplawski wrote:
> > 
> > I've thought e.g. about "fasteoi" for this "Virtual Wire" timer for
> > i386: I hope it's OK, but since is it any problem to add some comment
> > here, why it's OK with resending here (with POWERPC it's easier to
> > think it's something special, but here we have to similar things in
> > the same file)?

Sorry! Of course, there is something about edge in a lapic_chip
declaration, so this (plus some knowledge of the subject) should be
enough, but I was a little surprised that x86_64 uses handle_edge_irq
for probably(?) the same thing.

> 
> To be totally fair, there shouldn't be a problem with spurrious
> re-sends, I'm not sure what problems some chipsets are having there,
> though it may be related to the method used for re-sending. On ppc, we
> use the soft method I think everywhere anyway.

IMHO, this method is very doubtful if the whole system isn't adapted
for this: e.g. in networking code softirqs are blocked very often, so
such resended irq could be really late.

> 
> I use re-sending on cell with fasteoi for the on-die top-level PIC
> because while it does have a HW priority handling, it also doesn't have
> a HW mask. Thus I just "drop" IRQs that are masked and resend (it's edge
> messages).

So, if I got this right, it looks a bit easier, since you can resend with
the same type as not masked ones (fasteoi-edge?!), I guess.

Regards,
Jarek P.
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