Geode hardware requires no delay when doing power transition for PCI;
the board doesn't even have a real PCI bus. Thanks to Tom Sylla for
pointing this out. We can save precious milliseconds when changing power
states to D3hot by getting rid of this delay.
We do this as a PCI quirk.
Signed-off-by: Andres Salomon <[email protected]>
---
drivers/pci/quirks.c | 14 ++++++++++++++
1 files changed, 14 insertions(+), 0 deletions(-)
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 01d8f8a..b85fd5f 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -1368,6 +1368,20 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm);
/*
+ * Geode hardware does not require any sort of delay when
+ * transitioning between PCI power states. This allows us to shave
+ * off time when doing suspend/resume.
+ */
+static void __init quirk_geode_pci_pm(struct pci_dev *dev)
+{
+ pci_pm_d3_delay = 0;
+}
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5530_LEGACY,
+ quirk_geode_pci_pm);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA,
+ quirk_geode_pci_pm);
+
+/*
* Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size
* but the PIO transfers won't work if BAR0 falls at the odd 8 bytes.
* Re-allocate the region if needed...
-
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