At Mon, 14 May 2007 16:40:02 +0200, Arnd Bergmann wrote:
> > +#if defined(CONFIG_PPC_CELLEB) && defined(CONFIG_PREEMPT_RT)
> > +/* Since tlb flush takes long time on Celleb, reduce it to 1 when Celleb && RT */
> > +#define PPC64_TLB_BATCH_NR 1
> With this code, you get silent side-effects of enabling PPC_CELLEB
> along with another platform.
> Maybe instead you should change the hpte_need_flush() to always flush
> when running on the celleb platform and PREEMPT_RT is enabled.
OK, how about this one?
thanks a lot!
Since flushing tlb needs expensive hypervisor call(s) on celleb,
always flush it on RT to reduce scheduling latency.
Signed-off-by: Tsutomu OWA <[email protected]>
-- owa
--- linux-2.6.21-rt1/arch/powerpc/mm/tlb_64.c 2007-05-07 14:08:12.000000000 +0900
+++ rt/arch/powerpc/mm/tlb_64.c 2007-05-15 15:19:34.000000000 +0900
@@ -31,6 +31,7 @@
#include <asm/tlbflush.h>
#include <asm/tlb.h>
#include <asm/bug.h>
+#include <asm/machdep.h>
DEFINE_PER_CPU(struct ppc64_tlb_batch, ppc64_tlb_batch);
@@ -180,6 +181,18 @@ void hpte_update(struct mm_struct *mm, u
batch->vaddr[i] = (vsid << 28 ) | (addr & 0x0fffffff);
batch->pte[i] = __real_pte(__pte(pte), ptep);
batch->index = ++i;
+
+#ifdef CONFIG_PREEMPT_RT
+ /*
+ * Since flushing tlb needs expensive hypervisor call(s) on celleb,
+ * always flush it on RT to reduce scheduling latency.
+ */
+ if (machine_is(celleb)) {
+ flush_tlb_pending();
+ return;
+ }
+#endif /* CONFIG_PREEMPT_RT */
+
if (i >= PPC64_TLB_BATCH_NR)
flush_tlb_pending();
}
-
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