To reduce scheduling latecy by changing tlb flush size to 1.
Since tlb flush on Celleb is done by calling (an) expensive hypervisor call(s),
it takes a long time to flush tlbs and causes scheduing latency.
As I don't know how long it takes on other platforms, it would be better to
enclose it within #ifdef CONFIG_PPC_CELLEB.
Signed-off-by: Tsutomu OWA <[email protected]>
-- owa
diff -rup linux-2.6.21-rt1/include/asm-powerpc/tlbflush.h rt/include/asm-powerpc/tlbflush.h
--- linux-2.6.21-rt1/include/asm-powerpc/tlbflush.h 2007-04-26 12:08:32.000000000 +0900
+++ rt/include/asm-powerpc/tlbflush.h 2007-05-07 14:23:50.000000000 +0900
@@ -25,7 +25,11 @@ struct mm_struct;
#include <linux/percpu.h>
#include <asm/page.h>
+#ifdef CONFIG_PREEMPT_RT
+#define PPC64_TLB_BATCH_NR 1 /* Since tlb flush takes long time, reduce it to 1 when RT */
+#else
#define PPC64_TLB_BATCH_NR 192
+#endif /* CONFIG_PREEMPT_RT */
struct ppc64_tlb_batch {
unsigned long index;
-
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